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11.3 gbps, active back-termination, differential vcsel driver ADN2530 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features up to 11.3 gbps operation ?40c to +100c operation very low power: i supply = 65 ma typical 26 ps rise/fall times full back-termination of output transmission lines crosspoint adjust function pecl-/cml-compatible data inputs bias current range: 2 ma to 25 ma differential modulation current range: 2.2 ma to 23 ma automatic laser shutdown (als) 3.3 v operation compact 3 mm 3 mm lfcsp voltage-input control for bias and modulation currents xfp-compliant bias current monitor applications 10 gb ethernet optical transceivers 10g-base-lrm optical transceivers 8 and 10 fibre channel optical transceivers xfp/x2/xenpak/msa 300 optical modules sonet oc-192/sdh stm-64 optical transceivers general description the ADN2530 laser diode driver is designed for direct modula- tion of packaged vcsels with a differential resistance ranging from 35 to 140 . the active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. the back-termination in the adn25 30 absorbs signal reflections from the tosa end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the tosa end of the output transmission lines is significantly misterminated. the small package provides the optimum solution for compact modules where laser diodes are packaged in low pin count optical subassemblies. the modulation and bias currents are programmable via the mset and bset control pins. by driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. the eye crosspoint in the output eye diagram is adjustable via the crosspoint adjust (cpa) control voltage input. the automatic laser shutdown (als) feature allows the user to turn on/off the bias and modulation currents by driving the als pin with the proper logic levels. the product is available in a space-saving 3 mm 3 mm lfcsp specified from ?40c to +100c. functional block diagram 05457-001 100 ? 200 ? 800 ? 200 ? 10 ? vcc datap datan mset gnd bset ibmon ibias imodp imodn ADN2530 v cc a ls gnd vcc vcc 50 ? 50? cp a 200 ? 800 ? cross point adjust imod figure 1. 4 .com u datasheet
ADN2530 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 package thermal specifications ................................................. 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 input stage................................................................................... 10 bias current ................................................................................ 10 automatic laser shutdown (als) ........................................... 11 modulation current................................................................... 11 load mistermination ................................................................. 13 crosspoint adjust....................................................................... 13 power consumption .................................................................. 13 applications information .............................................................. 15 typical application circuit....................................................... 15 layout guidelines....................................................................... 15 design example.......................................................................... 16 headroom calculations ........................................................ 16 bset and mset pin voltage calculation .......................... 16 ibias monitor accuracy calculations................................ 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 8/06rev. 0 to rev. a changes to figure 1.......................................................................... 1 changes to table 3............................................................................ 5 changes to figure 24...................................................................... 10 changes to figure 30...................................................................... 11 changes to modulation current section .................................... 12 changes to typical application circuit section......................... 15 10/05revision 0: initial version 4 .com u datasheet
ADN2530 rev. a | page 3 of 20 specifications vcc = vcc min to vcc max , t a = ?40c to +100c, 100 differential load impedance, crosspoint adjust disabled, unless otherwise noted. typical values are specified at 25c and imod = 10 ma with crosspoint adjust disabled, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments bias current (ibias) bias current range 2 25 ma bias current while als asserted 50 a als = high compliance voltage 1 0.55 vcc C 1.3 v ibias = 25 ma 0.55 vcc C 0.8 v ibias = 2 ma modulation current (imodp, imodn) modulation current range 2.2 23 ma diff r load = 35 to 100 differential 2.2 19 ma diff r load = 140 differential modulation current while als asserted 250 a diff als = high crosspoint adjust (cpa) range 2 35 65 % rise time (20% to 80%) 2 , 3 , 4 26 32.5 ps cpa disabled 26.4 34.7 ps cpa 35% to 65% fall time (20% to 80%) 2 , 3 , 4 26 32.5 ps cpa disabled 26.5 33.7 ps cpa 35% to 65% random jitter 2 , 3 , 4 <0.5 ps rms cpa disabled <0.5 ps rms cpa 35% to 65% deterministic jitter 2 , 4 , 5 5.4 8.2 ps p-p 10.7 gbps, cpa disabled 5.8 8.2 ps p-p 10.7 gbps, cpa 35% to 65% deterministic jitter 2 , 4 , 6 5.4 8.2 ps p-p 11.3 gbps, cpa disabled 5.8 8.2 ps p-p 11.3 gbps, cpa 35% to 65% differential |s22| ?5 db 5 ghz < f < 10 ghz, z 0 = 100 differential ?13.6 db f < 5 ghz, z 0 = 100 differential compliance voltage 1 vcc ? 0.7 vcc + 0.7 v data inputs (datap, datan) input data rate 11.3 gbps nrz differential input swing 0.4 1.6 v p-p diff differential ac-coupled differential |s11| ?15 db f < 10 ghz, z 0 = 100 differential input termination resistance 85 100 115 differential bias control input (bset) bset voltage to ibias gain 15 20 24 ma/v bset input resistance 800 1000 1200 modulation control input (mset) mset voltage to imod gain 14 19 23 ma/v mset input resistance 800 1000 1200 bias monitor (ibmon) ibmon to ibias ratio 50 a/ma accuracy of ibias to ibmon ratio ?5.0 +5.0 % ibias = 2 ma, r ibmon = 750 ?4.3 +4.3 % ibias = 4 ma, r ibmon = 750 ?3.5 +3.5 % ibias = 8 ma, r ibmon = 750 ?3.0 +3.0 % ibias = 14 ma, r ibmon = 750 ?2.5 +2.5 % ibias = 25 ma, r ibmon = 750 automatic laser shutdown (als) v ih 2.4 v v il 0.8 v i il ?20 +20 a i ih 0 200 a 4 .com u datasheet
ADN2530 rev. a | page 4 of 20 parameter min typ max unit test conditions/comments als assert time 2 s rising edge of als to fall of ibias and imod below 10% of nominal; see figure 2 als negate time 10 s falling edge of als to rise of ibias and imod above 90% of nominal; see figure 2 power supply v cc 3.07 3.3 3.53 v i cc 7 27 32 ma v bset = v mset = 0 v i supply 8 65 76 ma v bset = v mset = 0 v 1 the voltage between the pin with the sp ecified compliance voltage and gnd. 2 specified for t a = ?40c to +85c due to test equipment limitation. see the typi cal performance characteristics section for data on performance for t a = ?40c to +100c. 3 the pattern used is composed of a repetitive sequen ce of eight 1s followed by eight 0s at 10.7 gbps. 4 measured using the high speed characterization circuit sh own in figure 3. 5 the pattern used is k28.5 (00111110101100000101) at 10.7 gbps rate. 6 the pattern used is k28.5 (00111110101100000101) at 11.3 gbps rate. 7 only includes current in the ADN2530 vcc pins. 8 includes current in ADN2530 vcc pins and dc current in imodp and imodn pull-up inductors. see the powe r consumption section fo r total supply current calculation. package thermal specifications table 2. parameter min typ max unit conditions/comments j-top 65 72.2 79.4 c/w thermal resistance from junction to top of package. j-pad 2.6 5.8 10.7 c/w thermal resistance from junction to bottom of exposed pad. ic junction temperature 125 c 90% 10% als ibias and imod als assert time als negate time t t 05457-002 figure 2. als timing diagram mset cpa als gnd bset ibmon ibias gnd vcc imodp imodn vcc j8 j5 vee vee tp1 10nf ADN2530 10 f vee gnd gnd gnd gnd gnd gnd gnd gnd gnd 50 50 oscilloscope bias tee: picosecond pulse labs model 5542-219 adapter: pasternack pe-9436 2.92mm female-to-female adapter attenuator: pasternack pe-7046 2.92mm 10db attenuator dc-block: agilent blocking capacitor 11742a adapter vbset z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 750 vee vee vmset gnd gnd gnd vee vcpa tp2 10 10nf gnd vee j2 gnd gnd gnd gnd vcc vcc datan datap gnd gnd gnd j3 gnd gnd bias tee bias tee adapter attenuator attenuator 05457-003 dc-block dc-block figure 3. high speed characterization circuit 4 .com u datasheet
ADN2530 rev. a | page 5 of 20 absolute maximum ratings table 3. parameter rating supply voltagevcc to gnd ?0.3 v to +4.2 v imodp, imodn to gnd vcc ? 1.5 v to +4.5 v datap, datan to gnd vcc ? 1.8 v to vcc ? 0.4 v all other pins ?0.3 v to vcc + 0.3 v junction temperature 150c storage temperature range ?65c to +150c soldering temperature (less than 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality. 4 .com u datasheet
ADN2530 rev. a | page 6 of 20 pin configuration and fu nction descriptions 05457-004 12 11 10 9 gnd ibias ibmon bset 1 mset 2 3 5 vcc imodn imodp vcc 6 7 8 4 gnd als cpa 16 15 14 13 ADN2530 top view (not to scale) pin 1 indicator vcc datan datap vcc notes: there is an exposed pad on the bottom of the package that must b e connected to the vcc or gnd plane. figure 4. pin configuration table 4. pin function descriptions pin o. neonic i/ description 1 mset input modulation current control input 2 cpa input crosspoint adjust control input 3 als input automatic laser shutdown 4 gnd power negative power supply 5 vcc power positive power supply 6 imodn output modulation current negative output 7 imodp output modulation current positive output 8 vcc power positive power supply 9 gnd power negative power supply 10 ibias output bias current output 11 ibmon output bias curr ent monitoring output 12 bset input bias current control input 13 vcc power positive power supply 14 datap input data signal positive input 15 datan input data signal negative input 16 vcc power positive power supply exposed pad pad power connect to gnd or vcc 4 .com u datasheet
ADN2530 rev. a | page 7 of 20 typical performance characteristics t a = 25c, vcc = 3.3 v, crosspoint adjust disabled, unless otherwise noted. 05457-035 0 0 30 25 20 15 10 5 25 20 15 10 5 differential modulation current (ma) rise time (ps) figure 5. rise time vs. imod 05457-036 0 0 5 10 15 20 25 30 25 20 15 10 5 differential modulation current (ma) fall time (ps) figure 6. fall time vs. imod 05457-049 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 151413121110987654321 frequency (ghz) differential |s11| (db) figure 7. differential |s11| 05457-037 0 0 1 2 3 4 5 6 7 8 9 10 25 10.7gbps 11.3gbps 20 15 10 5 differential modulation current (ma) deterministic jitter (ps) figure 8. determinis tic jitter vs. imod 05457-048 0 0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 25 20 15 10 5 differential modulation current (ma) random jitter (ps rms) jitter below equipment measurement capability figure 9. random jitter vs. imod 05457-050 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 151413121110987654321 frequency (ghz) differential |s22| (db) figure 10. differential |s22| 4 .com u datasheet
ADN2530 rev. a | page 8 of 20 05457-044 ?40 0 5 10 15 20 25 30 35 100 80 60 40 20 0 ?20 temperature (c) rise time (ps) figure 11. rise time vs. temperature (worse-case conditions, cpa disabled) 05457-045 ?40 0 5 10 15 20 25 30 35 100 80 60 40 20 0 ?20 temperature (c) fall time (ps) figure 12. fall time vs. temperature (worst-case conditions, cpa disabled) 05457-046 ?40 0 0.2 0.4 0.6 0.8 1.0 100 80 60 40 20 0 ?20 temperature (c) random jitter (ps rms) figure 13. random jitter vs. temperature (worst-case conditions, cpa disabl ed [worst-case imod = 2.2 ma]) 05457-047 ?40 0 10 9 8 7 6 5 4 3 2 1 100 80 60 40 20 0 ?20 temperature (c) deterministic jitter (ps) 10.7gbps 11.3gbps figure 14. deterministic jitter vs. temperature (worse-case conditions, cpa disabled) 05457-042 1.00 20 30 40 50 60 70 80 2.50 2.25 2.00 1.75 1.50 1.25 cpa voltage (v) imod eye crosspoint (%) vcc = [3.07, 3.3, 3.53] figure 15. imod eye diagram crosspoint vs. cpa voltage and vcc (imod = 10 ma) 05457-043 0.75 20 30 40 50 60 70 80 2.50 2.25 2.00 1.75 1.50 1.25 1.00 cpa voltage (v) imod eye crosspoint (%) +100c +85c +25c ?40c figure 16. imod eye diagram crosspoint vs. cpa voltage and temperature (imod = 10 ma) 4 .com u datasheet
ADN2530 rev. a | page 9 of 20 05457-038 0 0 20 40 80 60 100 120 140 25 20 15 10 5 differential modulation current (ma) total supply current (ma) ibias = 25ma ibias = 10ma ibias = 2ma figure 17. total supply current vs. imod 05457-039 26 0 5 10 15 20 25 31 30 29 28 27 rise time (ps) occurance (%) figure 18. worst-case rise time distribution 05457-040 26 0 5 10 15 20 25 31 30 29 28 27 fall time (ps) occurance (%) figure 19. worst-case fall time distribution 05457-014 1 level 1 level 0 level 0 level crossing figure 20. electrical eye diagram (imod = 10 ma, prbs31 pattern at 10.3125 gbps) 05457-016 figure 21. filtered 10g ethernet optical eye using aoc hfe6192-562 vcsel (prbs31 pattern at 10.3125 gbps, 3 db optical attenuator) 4 .com u datasheet
ADN2530 rev. a | page 10 of 20 theory of operation as shown in figure 1 , the ADN2530 consists of an input stage and two voltage-controlled current sources for bias and modulation. the bias current is available at the ibias pin. it is controlled by the voltage at the bset pin and can be monitored at the ibmon pin. the differential modulation current is available at the imodp and imodn pins. it is controlled by the voltage at the mset pin. the output stage implements the active back-termination circuitry for proper transmission line matching and power consumption reduction. the ADN2530 can drive a load with differential resistance ranging from 35 to 140 . the excellent back -termination in the ADN2530 absorbs signal reflections from the tosa end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the tosa end of the output transmission lines is significantly misterminated. input stage the input stage of the ADN2530 converts the data signal applied to the datap and datan pins to a level that ensures proper operation of the high speed switch. the equivalent circuit of the input stage is shown in figure 22 . vcc 50 50 vcc data p datan vcc 05457-017 figure 22. equivalent circuit of the input stage the datap and datan pins are terminated internally with a 100 differential termination resistor. this minimizes signal reflections at the input that could otherwise lead to degradation in the output eye diagram. it is not recommended to drive the ADN2530 with single-ended data signal sources. the ADN2530 input stage must be ac-coupled to the signal source to eliminate the need for matching between the common- mode voltages of the data signal source and the input stage of the driver (see figure 23 ). the ac-coupling capacitors should have an impedance less than 50 over the required frequency range. generally, this is achieved using 10 nf to 100 nf capacitors. ADN2530 datap datan c c 50 50 data signal source 05457-018 figure 23. ac coupling the data source to the ADN2530 data inputs bias current the bias current is generated internally using a voltage-to-current converter consisting of an internal operational amplifier and a transistor, as shown in figure 24 . gnd 200? 800? 10 ? vcc ibmon bset ibmon ADN2530 ibias 200 ? ibias 0 5457-019 figure 24. voltage-to-current converter used to generate ibias the bset to ibias voltage-to-current conversion factor is set at 20 ma/v by the internal resistors, and the bias current is monitored at the ibmon pin using a current mirror with a gain equal to 1/20. by connecting a 750 resistor between ibmon and gnd, the bias current can be monitored as a voltage across the resistor. a low temperature coefficient precision resistor must be used for the ibmon resistor (r ibmon ). any error in the value of r ibmon due to tolerances or drift in its value over temperature contributes to the overall error budget for the ibias monitor voltage. if the ibmon voltage is being connected to an adc for a/d conversion, r ibmon should be placed close to the adc to minimize errors due to voltage drops on the ground plane. see the design example section for example calculations of the accuracy of the ibias monitor as a percentage of the nominal ibias value. 4 .com u datasheet
ADN2530 rev. a | page 11 of 20 the equivalent circuits of the bset, ibias, and ibmon pins are shown in figure 25 to figure 27 . vcc bset vcc 800 200 05457-020 figure 25. equivalent ci rcuit of the bset pin 10 2k 100 ibias vcc vcc 05457-021 figure 26. equivalent ci rcuit of the ibias pin vcc ibmon vcc 100 500 vcc 05457-022 figure 27. equivalent ci rcuit of the ibmon pin the recommended configuration for bset, ibias, and ibmon is shown in figure 28 . ADN2530 bset vbset gnd ibmon ibias to laser cathode l r ibmon 750 ibias 05457-023 figure 28. recommended configuratio n for bset, ibias, and ibmon pins the circuit used to drive the bset voltage must be able to drive the 1 k input resistance of the bset pin. for proper operation of the bias current source, the voltage at the ibias pin must be between the compliance voltage specifications for this pin over supply, temperature, and bias current range (see table 1 ). the maximum compliance voltage is specified for only two bias current levels (2 ma and 25 ma), but it can be calculated for any bias current by v compliance (v) = vcc (v) ? 0.75 ? 22 ibias (a) see the headroom calculations section for examples. the function of inductor l is to isolate the capacitance of the ibias output from the high frequency signal path. for recommended components, see table 6 . automatic laser shutdown (als) the als pin is a digital input that enables/disables both the bias and modulation currents, depending on the logic state applied, as shown in table 5 . table 5. als logic state ibias and imod high disabled low enabled floating enabled the als pin is compatible with 3.3 v cmos and ttl logic levels. its equivalent circuit is shown in figure 29 . v cc als v cc 100 35k 2k 05457-024 figure 29. equivalent circuit of the als pin modulation current the modulation current can be controlled by applying a dc voltage to the mset pin. this voltage is converted into a dc current by using a voltage-to-current converter that uses an operational amplifier and a bipolar transistor, as shown in figure 30 . 100 ? 200 ? 800 ? mset gnd imodp imodn ADN2530 vcc from cpa stage 0 5457-025 imod figure 30. generation of modulation current on the ADN2530 this dc current is switched by the data signal applied to the input stage (datap and datan pins) and gained up by the output stage to generate the differential modulation current at the imodp and imodn pins. the output stage also generates the active back-termination, which provides proper transmission line termination. active back-termination uses feedback around an active circuit to synthesize a broadband termination resistance. 4 .com u datasheet
ADN2530 rev. a | page 12 of 20 this provides excellent transmission line termination while dissipating less power than a traditional resistor passive back- termination. no portion of the modulation current flows in the active back-termination resistance. all of the preset modulation current imod, the range specified in table 1 , flows in the external load. the equivalent circuits for mset, imodp, and imodn are shown in figure 31 and figure 32 . the two 50 resistors in figure 32 are not real resistors. they represent the active back-termination resistance. v cc mset 800 200 v cc 05457-026 figure 31. equivalent ci rcuit of the mset pin vcc vcc 15 15 50 imodp imodn 50 05457-027 figure 32. equivalent circuit of the imodp and imodn pins the recommended configuration of the mset, imodp, and imodn pins is shown in figure 33 . see table 6 for recom- mended components. when the voltage on datap is greater than the voltage on datan, the modulation current flows into the imodp pin and out of the imodn pin, generating an optical logic 1 level at the tosa output when the tosa is connected as shown in figure 33 . 05457-028 ADN2530 mset vmset gnd imodn imodp c tosa z 0 = 50 z 0 = 50 c z 0 = 50 z 0 = 50 l vcc l vcc vcc l l ibias figure 33. recommended configuration for the mset, imodp, and imodn pins the ratio between the voltage applied to the mset pin and the differential modulation current available at the imodp and imodn pins is a function of the load resistance value, as shown in figure 34 . 05457-029 10 10 45 40 35 30 25 20 15 1401301201101009080706050403020 differential load resistance mset voltage to modulation current ratio (ma/v) max typ min figure 34. mset voltage to modulation current ratio vs. differential load resistance using the resistance of the tosa, the user can calculate the voltage range that should be applied to the mset pin to generate the required modulation current range (see the example in the applications information section). the circuit used to drive the mset voltage must be able to drive the 1 k resistance of the mset pin. to be able to drive 23 ma modulation currents through the differential load, the output stage of the ADN2530 (imodp and imodn pins) must be ac-coupled to the load. the voltages at these pins have a dc component equal to vcc and an ac component with single-ended peak-to-peak amplitude of imod 50 . this is the case when the load impedance (r tosa ) is less than 100 differential because the transmission line characteristic impedance sets the peak-to-peak amplitude. for the case where r tosa is greater than 100 , the single-ended, peak-to-peak amplitude is imod r tosa 2. for proper operation of the output stage, the voltages at the imodp and imodn pins must be between the compliance voltage specifications for this pin over supply, temperature, and modulation current range, as shown in figure 35 . see the headroom calculations section for examples of headroom calculations. v imodp, v imodn vcc vcc ? 0.7v vcc + 0.7v normal operation region 05457-030 figure 35. allowable range for the voltage at imodp and imodn 4 .com u datasheet
ADN2530 rev. a | page 13 of 20 load mistermination due to its excellent s22 performance, the ADN2530 can drive differential loads that range from 35 to 140 . in practice, many tosas have differential resistance not equal to 100 . in this case, with 100 differential transmission lines connecting the ADN2530 to the load, the load end of the transmission lines are misterminated. this mistermination leads to signal reflections back to the driver. the excellent back-termination in the ADN2530 absorbs these reflections, preventing their reflection back to the load. this enables excellent optical eye quality to be achieved even when the load end of the transmission lines is significantly misterminated. the connection between the load and the ADN2530 must be made with 100 differential (50 single-ended) transmission lines so that the driver end of the transmission lines is properly terminated. crosspoint adjust the crossing level in the output electrical eye diagram can be adjusted between 35% and 65% using the crosspoint adjust (cpa) control input. this can be used to compensate for asymmetry in the vcsel response and optimizes the optical eye mask margin. the cpa input is a voltage control input, and a plot of eye cross- point vs. cpa control voltage is shown in figure 15 and figure 16 in the typical performance characteristics section. the equivalent circuit for the cpa pin is shown in figure 36 . to disable the crosspoint adjust function and set the eye crossing to 50%, the cpa pin should be tied to vcc. 05457-031 100 vcc cpa figure 36. equivalent circuit for cpa pin power consumption the power dissipated by the ADN2530 is given by )2.1( 50 + ? ? ? ? ? ? += where: vcc is the power supply voltage. ibias is the bias current generated by the ADN2530. v mset is the voltage applied to the mset pin. i suppl is the sum of the current that flows into the vcc, imodp, and imodn pins of the ADN2530 when ibias = imod = 0 expressed in amps (see table 1 ). v ibias is the average voltage on the ibias pin. considering vbset/ibias = 50 as the conversion factor from v bset to ibias, the dissipated power becomes ? ? ? ? ? ? + ? ? ? ? ? ? += 2.1 50 50 bset ibias suppl mset v vi v vccp to ensure long-term reliable operation, the junction tempera- ture of the ADN2530 must not exceed 125c, as specified in table 2 . for improved heat dissipation, the modules case can be used as a heat sink, as shown in figure 37 . t top t j t pad die package thermal compound module case pcb vias copper plane thermo-couple 05457-032 figure 37. typical optical module structure 4 .com u datasheet
ADN2530 rev. a | page 14 of 20 p j-top t pad t top t top j-pad t pad t j 05757-033 a compact optical module is a complex thermal environment, and calculations of device junction temperature using the package ja (junction-to-ambient thermal resistance) do not yield accurate results. the following equation, derived from the model in figure 38 , can be used to estimate the ic junction temperature: ( ) topj padj topj pad padj top topj padj j t t p t ? ? ? ? ? ? + ?+?+?? = figure 38. electrical model for thermal calculations where: t top and t pad can be determined by measuring the temperature at points inside the module, as shown in figure 37 . the thermo- couples should be positioned to obtain an accurate measurement of the package top and paddle temperatures. j-top and j-pad are given in table 2 . t top is the temperature at top of package in degrees celsius. t pad is the temperature at package exposed paddle in degrees celsius. t j is the ic junction temperature in degrees celsius. p is the ADN2530 power dissipation in watts. j-top is the thermal resistance from ic junction to package top. j-pad is the thermal resistance from ic junction to package exposed pad. 4 .com u datasheet
ADN2530 rev. a | page 15 of 20 applications information typical application circuit figure 39 shows the typical application circuit for the ADN2530. the dc voltages applied to the bset and mset pins control the bias and modulation currents. the bias current can be monitored as a voltage drop across the 750 resistor connected between the ibmon pin and gnd. the dc voltage applied to the cpa pin controls the crosspoint in the output eye diagram. by tying the cpa pin to vcc, the cpa function is disabled. the als pin allows the user to turn on/off the bias and modulation currents depending on the logic level applied to the pin. the data signal source must be connected to the datap and datan pins of the ADN2530 using 50 transmission lines. the modulation current outputs, imodp and imodn, must be connected to the load (tosa) using 100 differential (50 single-ended) transmission lines. table 6 shows recommended components for the ac-coupling interface between the ADN2530 and tosa. for additional application information and optical eye diagram performance data, see the application notes and reference design for the ADN2530 at www.analog.com . table 6. component value description r1, r2 110 0603 size resistor r3, r4 300 0603 size resistor c3, c4 100 nf 0402 size capacitor, phycomp 223878719849 l6, l7 160 nh 0603 size inductor, murata lqw18anr16 l2, l3 0603 size chip ferrite bead, murata blm18hg601 l1, l4, l5, l8 10 h 0805 size inductor, murata lqm21fn100m70l layout guidelines due to the high frequencies at which the ADN2530 operates, care should be taken when designing the pcb layout to obtain optimum performance. controlled impedance transmission lines must be used for the high speed signal paths. the length of the transmission lines must be kept to a minimum to reduce losses and pattern-dependent jitter. the pcb layout must be symmetrical both on the datap and datan inputs and on the imodp and imodn outputs to ensure a balance between the differential signals. all vcc and gnd pins must be connected to solid copper planes by using low inductance connections. when the connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. each gnd pin must be locally decoupled to vcc with high quality capacitors, see figure 39 . if proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each gnd pin. a 20 f tantalum capacitor must be used as the general decoupling capacitor for the entire module. for recommended pcb layouts, including those suitable for xfp modules, contact sales. for guidelines on the surface-mount assembly of the ADN2530, consult the amkor technology? application notes for surface mount assembly of amkors micro leadframe? (mlf?) packages. mset als gnd bset ibmon ibias gnd vcc datap datan vcc vcc imodp imodn vcc datap datan c1 c2 mset bset r5 750 ADN2530 z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 gnd vcc gnd vcc tosa c4 c7 20 f l2 l1 r1 +3.3v vcc vcc vcc vcc vcc tp1 c5 10nf gnd gnd vcc c6 10nf gnd als cpa cpa l7 l8 r4 l6 l5 r3 vcc l3 l4 r2 vcc z 0 = 50 z 0 = 50 c3 gnd 05757-034 v cc c8 100nf figure 39. typical ADN2530 application circuit 4 .com u datasheet
ADN2530 rev. a | page 16 of 20 design example this design example covers: ? headroom calculations for ibias, imodp, and imodn pins. ? calculation of the typical voltage required at the bset and mset pins to produce the desired bias and modulation currents. ? calculations of the ibias monitor accuracy over the ibias current range. this design example assumes that the impedance of the tosa is 60 , the forward voltage of the vcsel at low current is v f = 1.2 v, ibias = 10 ma, imod = 10 ma, and vcc = 3.3 v. headroom calculations to ensure proper device operation, the voltages on the ibias, imodp, and imodn pins must meet the compliance voltage specifications in table 1 . considering the typical application circuit shown in figure 39 , the voltage at the ibias pin can be written as v ibias = vcc ? v f ? ( ibias r tosa ) ? v la where: vcc is the supply voltage. v f is the forward voltage across the laser at low current. r tosa is the resistance of the tosa. v la is the dc voltage drop across l5, l6, l7, and l8. for proper operation, the minimum voltage at the ibias pin should be greater than 0.55 v, as specified by the minimum ibias compliance specification in table 1 . assuming that the voltage drop across the 50 transmission lines is negligible and that v la = 0 v, v f = 1.2 v, and ibias = 10 ma, v ibias = 3.3 ? 1.2 ? (0.01 60) = 1.5 v v ibias = 1.5 v > 0.55 v , which satisfies the requirement the maximum voltage at the ibias pin must be less than the maximum ibias compliance specification as described by v compliance_max = vcc ? 0.75 ? 22 ibias (a) for this example, v compliance_max = vcc C 0.75 ? 22 0.01 = 2.33 v v ibias = 1.5 v < 2.33 v , which satisfies the requirement to calculate the headroom at the modulation current pins (imodp and imodn), the voltage has a dc component equal to vcc due to the ac-coupled configuration and a swing equal to imod 50 , as r tosa < 100 . for proper operation of the ADN2530, the voltage at each modulation output pin should be within the normal operation region shown in figure 35 . assuming the dc voltage drop across l1, l2, l3, and l4 = 0 v and imod = 10 ma, the minimum voltage at the modulation output pins is equal to vcc ? ( imod 50)/2 = vcc ? 0.25 vcc ? 0.25 > vcc ? 0.7 v, which satisfies the requirement the maximum voltage at the modulation output pins is equal to vcc + ( imod 50)/2 = vcc + 0.25 vcc + 0.25 < vcc + 0.7 v, which satisfies the requirement headroom calculations must be repeated for the minimum and maximum values of the required ibias and imod ranges to ensure proper device operation over all operating conditions. bset and mset pin voltage calculation to set the desired bias and modulation currents, the bset and mset pins of the ADN2530 must be driven with the appropriate dc voltage. the voltage range required at the bset pin to generate the required ibias range can be calculated using the bset voltage to ibias gain specified in table 1 . assuming that ibias = 10 ma and the typical ibias/v bset ratio of 20 ma/v, the bset voltage is given by v5.0 20 10 ma/v20 (ma) == = the bset voltage range can be calculated using the required ibias range and the minimum and maximum bset voltage to ibias gain values specified in table 1. the voltage required at the mset pin to produce the desired modulation current can be calculated using k imod v mset = where k is the mset voltage to imod ratio. the value of k depends on the actual resistance of the tosa and can be obtained from figure 34 . for a tosa resistance of 60 , the typical value of k = 24 ma/v. assuming that imod = 10 ma and using the preceding equation, the mset voltage is given by v42.0 24 10 ma/v24 (ma) == = the mset voltage range can be calculated using the required imod range and the minimum and maximum k values. these can be obtained from the minimum and maximum curves in figure 34 . 4 .com u datasheet
ADN2530 rev. a | page 17 of 20 ibias monitor accuracy calculations 05457-041 0 0 1 2 3 4 5 6 25 20 15 10 5 ibias (ma) accuracy of ibias to ibmon ratio (%) figure 40. accuracy of ibias to ibmon ratio this example assumes that the nominal value of ibias is 8 ma and that the ibias range for all operating conditions is 4 ma to 14 ma. the accuracy of the ibias to ibmon ratio is given in the table 1 and is plotted in figure 40 . referring to figure 40 , the ibmon output current accuracy is 4.3% for the minimum ibias of 4 ma and 3.0% for the maximum ibias value of 14 ma. the accuracy of the ibmon output current as a percentage of the nominal ibias is given by %15.2 ma8 100 100 3.4 ma4 _ = = for the minimum ibias value, and by %25.5 ma8 100 100 0.3 ma14 _ = = for the maximum ibias value. this gives a worse-case accuracy for the ibmon output current of 5.25% of the nominal ibias value over all operating conditions. the ibmon output current accuracy numbers can be combined with the accuracy numbers for the 750 ibmon resistor (r ibmon ) and any other error sources to calculate an overall accuracy for the ibmon voltage. 4 .com u datasheet
ADN2530 rev. a | page 18 of 20 outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 41. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADN2530ycpz-wp 1 ?40c to +100c 16-lead lfcsp_vq, 50-piece waffle pack cp-16-3 f08 ADN2530ycpz-r2 1 ?40c to +100c 16-lead lfcsp_vq, 250-piece reel cp-16-3 f08 ADN2530ycpz-reel7 1 ?40c to +100c 16-lead lfcsp_vq, 1500-piece reel cp-16-3 f08 1 z = pb-free part. 4 .com u datasheet
ADN2530 rev. a | page 19 of 20 notes 4 .com u datasheet
ADN2530 rev. a | page 20 of 20 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05457C0C8/06(a) 4 .com u datasheet

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